FIG. 1A shows an equivalent circuit diagram of a conventional thyristor. It comprises an NPN bipolar transistor whose emitter forms the cathode C of the thyristor, and the base forms a low-side control terminal Pw. The collector of the NPN transistor is connected to the base of a PNP transistor. The base of the PNP transistor forms a high-side control terminal Nw. The emitter of the PNP transistor forms the anode A of the thyristor and the collector of the PNP transistor is connected to the base of the NPN transistor.
The thyristor is triggered (turned on) by drawing a current from the base of the PNP transistor through terminal Nw, or by injecting a current into the base of the NPN transistor through terminal Pw. Once the thyristor is triggered, it remains conductive even if the current through terminals Pw and Nw is canceled. Indeed, when the thyristor is on, the anode current is divided into two paths, one from the base of the PNP transistor to the collector of the NPN transistor, thereby maintaining the PNP transistor in its conductive state, and the other through the collector of the PNP transistor to the base of the NPN transistor, which maintains the NPN transistor in its conductive state.
FIG. 1B schematically shows a semiconductor structure of a conventional thyristor. A substrate Psub comprises two wells in lateral contact, a P-doped well Pwell, and an N-doped well Nwell. The top surface of well Pwell comprises an N+ doped region forming the cathode contact C, and a P+ doped region forming the low-side control terminal Pw. The top surface of well Nwell comprises, adjacent the cathode region C, a P+ doped region forming the anode contact A. The high-side control terminal Nw is formed by an N+ doped region of well Nwell. The N+ and P+ regions are separated by deep-trench insulations STI. Beneath the wells, there is a buried insulating layer Niso, and the remainder of substrate Psub.
The thyristor is formed in this structure by the junctions P-N-P-N going from the anode A to the cathode C. The NPN and PNP equivalent bipolar transistors are shown. Note that the two base-collector links between the transistors are actually formed in the single PN junction between the wells.
Thyristors are often used to protect integrated circuits against electrostatic discharges, and thus form part of the components that the designer may include in an integrated circuit. It may therefore be desirable that the electrical behavior of these thyristors can be simulated, as for the other components of the circuit, before finalizing the circuit for production.
The simulation of a thyristor involves difficulties. Indeed, in the case of a protection component, it is likely to be subjected to voltages and currents that are beyond the usual ranges of other circuit components.
In the so-called “small-signal” range, i.e. with currents and voltages within the normal circuit operation, the thyristor can be modeled by the two coupled transistors of the diagram of FIG. 1A.
However, once the thyristor is triggered, it is capable of short-circuiting low impedance terminals or deriving a voltage surge to ground, causing a current beyond the small signal range, i.e. beyond the validity limits of the original model. In the conventional small signal model of a bipolar transistor, the gain drops rapidly when the injection current, or collector current, exceeds a threshold. As a result, self-maintenance of the thyristor in its conducting state is no longer guaranteed beyond this threshold current.
FIG. 2 is a graph illustrating an exemplary evolution of the anode current IA as a function of the anode voltage VA (assuming the cathode voltage is zero) for a thyristor as it triggers.
The dotted curve corresponds to a real thyristor: upon triggering, the anode voltage falls rapidly to a minimum value while the anode current increases slightly. The thyristor then behaves as a low value resistance: the anode voltage increases slowly in proportion to the current.
The solid curve corresponds to a conventional small signal model: shortly after reaching the minimum anode voltage, the gains of the transistors fall rapidly. The right part of the figure shows the evolution of the gain βNPN of the NPN transistor. Initially, the gain is about 3.3. When this gain has fallen to a value close to 1, the transistors can no longer mutually maintain their conduction. The model tends to behave incorrectly as a low-value resistor in series with the voltage source supplying the anode.
The article [“Characterization and Modeling of SCR from DC down to CDM time domain”, Pascal Fonteneau et al., IEW 2008] discloses a model with two bipolar transistors, modified so that there is no gain degradation. Small signal behavior of this model is unsatisfactory, however.
Others have studied “binary” models, where switching is implemented between a small signal model and a strong current model, such as the papers (1) “A Novel Physical Model for the SCR ESD Protection Device”, Alexandru Romanescu et al., Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2010 and (2) “Scalable Modeling Studies on the SCR ESD Protection Device”, Alexandru Romanescu et al., EOS/ESD Symposium, 2011 33rd.
FIG. 3 schematically shows base elements of a model as described in the above Romanescu articles. Between the anode A and the cathode C, are successively connected: an anode resistor RA, an anode-N-well diode DANw (forward biased for a current which would flow from the anode to the cathode), a reverse biased N-well-P-well diode DNwPw, a forward biased P-well-cathode diode DPwC, and a cathode resistor RC. Between the anode A and the low-side control terminal Pw, are successively connected: resistor RA, a current source ITp, and a resistor RCTp. Between the high-side control terminal Nw and the cathode C, are successively connected: resistor RCTn, a current source ITn and resistor RC. A variable resistor RBp connects the cathode of diode DANw to resistor RCTn. A variable resistor RBn connects the anode of diode DPwC to resistor RCTp. A current source Ibk is connected in parallel with diode DNwPw.
Except for the diodes, FIG. 3 uses the same component designations as article (2), so direct reference to the equations of this article may be made for more detail on the model behavior. Article (2) actually provides two diodes in parallel for each diode in FIG. 3, i.e. diodes designated IBFp and IREp for diode DANw, diodes designated IBC and IRC for diode DNwPw, and diodes designated IBFn IREn for diode DPwC.
The diodes model the PN junctions of the structure of FIG. 1B. The current amplifying function of the bipolar transistors is modeled by equations governing the current sources ITp and ITn based on the Gummel-Poon equations. In these equations, modifier functions were introduced, denoted HCCFn for the NPN transistor and HCCFp for the PNP transistor. Each function HCCF is adjusted to switch the gain to a higher value when it reaches a value too low to maintain the thyristor on.
This approach requires the definition of several new parameters that have no physical meaning, e.g. the threshold, the slope and the magnitude of the gain switching. These parameters must be adjusted empirically, on a case-by-case basis. Since the switching function further introduces a discontinuity, simulations using this type of model may have convergence problems.